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» Saturation Effects in Testing of Formal Models
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EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
13 years 9 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
ICFEM
2007
Springer
13 years 9 months ago
Testing for Refinement in CSP
Abstract. CSP is a well-established formalism for modelling and verification of concurrent reactive systems based on refinement. Consolidated denotational models and an effective t...
Ana Cavalcanti, Marie-Claude Gaudel
ICST
2008
IEEE
13 years 11 months ago
Designing and Building a Software Test Organization
–Abstract for conference - preliminary Model-Based Testing: Models for Test Cases Jan Tretmans, Embedded Systems Institute, Eindhoven : Systematic testing of software plays an im...
Bruce Benton
UML
2001
Springer
13 years 9 months ago
Formalization of UML-Statecharts
The work presented here is part of a project that aims at the definition of a methodology for developing realtime software systems based on UML. In fact, being relatively easy to ...
Michael von der Beeck
HASE
2008
IEEE
13 years 5 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri