42 search results - page 1 / 9 » Scalable Hardware Memory Disambiguation for High ILP Process... |
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...