22 search results - page 3 / 5 » Scalable Test Generators for High-Speed Datapath Circuits |
DSD
2006
IEEE
14 years 3 days ago
2006
IEEE
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
VLSID
1997
IEEE
13 years 10 months ago
1997
IEEE
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
TCAD
2002
13 years 5 months ago
2002
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...
DATE
2007
IEEE
14 years 12 days ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
ATS
2003
IEEE
13 years 11 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...