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ISPA
2004
Springer
13 years 11 months ago
Cayley DHTs - A Group-Theoretic Framework for Analyzing DHTs Based on Cayley Graphs
Static DHT topologies influence important features of such DHTs such as scalability, communication load balancing, routing efficiency and fault tolerance. Nevertheless, it is co...
Changtao Qu, Wolfgang Nejdl, Matthias Kriesell
CCECE
2006
IEEE
13 years 11 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
VISUALIZATION
2005
IEEE
13 years 11 months ago
A Shader-Based Parallel Rendering Framework
Existing parallel or remote rendering solutions rely on communicating pixels, OpenGL commands, scene-graph changes or application-specific data. We propose an intermediate soluti...
Jérémie Allard, Bruno Raffin
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
13 years 9 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
WWW
2010
ACM
14 years 18 days ago
Mind the data skew: distributed inferencing by speeddating in elastic regions
Semantic Web data exhibits very skewed frequency distributions among terms. Efficient large-scale distributed reasoning methods should maintain load-balance in the face of such hi...
Spyros Kotoulas, Eyal Oren, Frank van Harmelen