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» Scaling, Power and the Future of CMOS
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VLSID
2007
IEEE
113views VLSI» more  VLSID 2007»
14 years 5 months ago
Scaling, Power and the Future of CMOS
Mark Horowitz
ICCD
2003
IEEE
165views Hardware» more  ICCD 2003»
14 years 1 months ago
CMOS High-Speed I/Os - Present and Future
High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technol...
M.-J. Edward Lee, William J. Dally, Ramin Farjad-R...
TVLSI
2008
99views more  TVLSI 2008»
13 years 4 months ago
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
Sheng-Chih Lin, Kaustav Banerjee
ICCD
2006
IEEE
148views Hardware» more  ICCD 2006»
14 years 1 months ago
Trends and Future Directions in Nano Structure Based Computing and Fabrication
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
R. Iris Bahar
CSREAESA
2007
13 years 6 months ago
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems
- Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active ...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...