87 search results - page 3 / 18 » Scaling Application Performance on a Cache-Coherent Multipro... |
DSD
2008
IEEE
13 years 7 months ago
2008
IEEE
Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory i...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
CF
2006
ACM
13 years 9 months ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
MAM
2002
13 years 5 months ago
2002
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...
MICRO
2007
IEEE
14 years 11 days ago
2007
IEEE
Snoopy cache coherence can be implemented in any physical network topology by embedding a logical unidirectional ring in the network. Control messages are forwarded using the ring...