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» Scaling and Packing on a Chip Multiprocessor
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IPPS
2007
IEEE
10 years 6 months ago
Scaling and Packing on a Chip Multiprocessor
Power management is critical in server and high-performancecomputing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support ...
Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Raw...
EUROPAR
2003
Springer
10 years 4 months ago
Exploiting On-Chip Data Transfers for Improving Performance of Chip-Scale Multiprocessors
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power eļ¬ƒcient, and easier to test and validate. In this work, we focus on a...
Guangyu Chen, Mahmut T. Kandemir, Alok N. Choudhar...
TCAD
2008
215views more  TCAD 2008»
9 years 11 months ago
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric
Abstract--This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an o...
Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho A...
CAL
2010
9 years 9 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
SAMOS
2004
Springer
10 years 5 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
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