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» Scan Test of IP Cores in an ATE Environment
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ATS
2010
IEEE
250views Hardware» more  ATS 2010»
13 years 2 months ago
Efficient Embedding of Deterministic Test Data
Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor techn...
Mudassar Majeed, Daniel Ahlstrom, Urban Ingelsson,...
CAI
2004
Springer
13 years 5 months ago
An Evolvable Combinational Unit for FPGAs
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
Lukás Sekanina, Stepan Friedl
DAC
2006
ACM
13 years 11 months ago
Design in reliability for communication designs
Silicon design implementation has become increasingly complex with the deep submicron technologies such as 90nm and below. It is common to see multiple processor cores, several ty...
Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar