9 search results - page 2 / 2 » Scheduling Register-Allocated Codes in User-Guided High-Leve... |
EGH
2005
Springer
13 years 11 months ago
2005
Springer
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...