17 search results - page 2 / 4 » Scheduling Reusable Instructions for Power Reduction |
ISSS
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
ISQED
2009
IEEE
14 years 1 days ago
2009
IEEE
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...
CF
2005
ACM
13 years 7 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...