4 search results - page 1 / 1 » Scheduling algorithm for partially parallel architecture of ... |
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
ICASSP
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...
ISCAS
2011
IEEE
12 years 8 months ago
2011
IEEE
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
VTC
2008
IEEE
13 years 11 months ago
2008
IEEE
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...