51 search results - page 9 / 11 » Scheduling and Binding Algorithms for High-Level Synthesis |
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...