123 search results - page 25 / 25 » Scheduling for power reduction in a real-time system |
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...