46 search results - page 3 / 10 » Self Testing SoC with Reduced Memory Requirements and Minimi... |
MTDT
2000
IEEE
13 years 9 months ago
2000
IEEE
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources i...
ISSS
1996
IEEE
13 years 9 months ago
1996
IEEE
An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the us...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
NPL
2006
13 years 4 months ago
2006
The authors previously proposed a self-organizing Hierarchical Cerebellar Model Articulation Controller (HCMAC) neural network containing a hierarchical GCMAC neural network and a ...