605 search results - page 1 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
IFIP
1993
Springer
13 years 9 months ago
1993
Springer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
IEEEPACT
1998
IEEE
13 years 9 months ago
1998
IEEE
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
DAC
2001
ACM
14 years 5 months ago
2001
ACM
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...