605 search results - page 3 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
ISSS
1996
IEEE
13 years 10 months ago
1996
IEEE
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...
IEEEPACT
2002
IEEE
13 years 10 months ago
2002
IEEE
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...