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ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
14 years 1 months ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
13 years 9 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
ISPD
1997
ACM
186views Hardware» more  ISPD 1997»
13 years 9 months ago
EWA: exact wiring-sizing algorithm
The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...
Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi
ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
13 years 11 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
ICCAD
1998
IEEE
93views Hardware» more  ICCAD 1998»
13 years 9 months ago
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong