7 search results - page 1 / 2 » Self-referential verification of gate-level implementations ... |
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
CADE
2009
Springer
14 years 6 months ago
2009
Springer
Scalable handling of real arithmetic is a crucial part of the verification of hybrid systems, mathematical algorithms, and mixed analog/digital circuits. Despite substantial advanc...