49 search results - page 8 / 10 » Sensitivity-Based Gate Delay Propagation in Static Timing An... |
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
DSD
2007
IEEE
14 years 3 days ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
MICRO
2007
IEEE
14 years 1 days ago
2007
IEEE
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...