18 search results - page 1 / 4 » Serial Sum-Product Architecture for Low-Density Parity-Check... |
ICCCN
2007
IEEE
13 years 11 months ago
2007
IEEE
—A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to c...
GLOBECOM
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardw...
GLOBECOM
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...