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ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
13 years 9 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
SIPS
2006
IEEE
13 years 11 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
ISMVL
2007
IEEE
112views Hardware» more  ISMVL 2007»
13 years 11 months ago
Survey of Stochastic Computation on Factor Graphs
Stochastic computation is a new alternative approach for iterative computation on factor graphs. In this approach, the information is represented by the statistics of the bit stre...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
TIT
2008
129views more  TIT 2008»
13 years 5 months ago
Serial Schedules for Belief-Propagation: Analysis of Convergence Time
Abstract--Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation algorithm over the factor graph of the code. In the traditional messa...
Jacob Goldberger, Haggai Kfir
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 5 months ago
Implementing LDPC Decoding on Network-on-Chip
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
Theo Theocharides, Greg M. Link, Narayanan Vijaykr...