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» Silicon Validation of Evolution-Designed Circuits
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GI
2009
Springer
13 years 10 months ago
Challenges of Electronic CAD in the Nano Scale Era
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets)...
Christian Hochberger, Andreas Koch
ISCAS
2003
IEEE
107views Hardware» more  ISCAS 2003»
13 years 11 months ago
On chip Gaussian processing for high resolution CMOS image sensors
Spatial image processing chips, known as silicon retinas, are based on the architecture of vertebrate retina and can be mathematically represented as the Laplacian of Gaussian (LO...
Sri Vinayagamoorthy, Richard Hornsey
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
13 years 10 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DAC
2009
ACM
14 years 6 months ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
DAC
2006
ACM
14 years 6 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin