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» Simulation Modeling at Multiple Levels of Abstraction
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APCSAC
2001
IEEE
13 years 9 months ago
Retargetable Cache Simulation Using High Level Processor Models
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
Rajiv A. Ravindran, Rajat Moona
ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
14 years 10 days ago
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
Bao Liu
TVCG
2010
151views more  TVCG 2010»
13 years 22 days ago
Interactive Visual Analysis of Multiple Simulation Runs Using the Simulation Model View: Understanding and Tuning of an Electron
Multiple simulation runs using the same simulation model with different values of control parameters usually generate large data sets that capture the variational aspects of the be...
Kresimir Matkovic, Denis Gracanin, Mario Jelovic, ...
DATE
2003
IEEE
134views Hardware» more  DATE 2003»
13 years 11 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
TVLSI
2008
152views more  TVLSI 2008»
13 years 5 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...