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ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
13 years 10 months ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Cycle error correction in asynchronous clock modeling for cycle-based simulation
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi
ECOWS
2006
Springer
13 years 8 months ago
Formal Modelling and Verification of an Asynchronous Extension of SOAP
Current web services are largely based on a synchronous request-response model that uses the Simple Object Access Protocol SOAP. Next-generation telecommunication networks, on the...
Maurice H. ter Beek, Stefania Gnesi, Franco Mazzan...
CL
2010
Springer
13 years 5 months ago
SystemJ: A GALS language for system level design
In this paper we present the syntax, semantics, and compilation of a new system-level programming language called SystemJ. SystemJ is a multiclock language supporting the Globally...
Avinash Malik, Zoran Salcic, Partha S. Roop, Alain...
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
13 years 9 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim