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» Simulation and modeling of the effect of substrate conductiv...
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3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
14 years 10 days ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
ICCD
2007
IEEE
124views Hardware» more  ICCD 2007»
14 years 2 months ago
Placement and routing of RF embedded passive designs in LCP substrate
Physical layout generation of RF embedded passive design is not an easy task since the response of a given layout is tightly coupled with the response of the individual components...
Mohit Pathak, Souvik Mukherjee, Madhavan Swaminath...
ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
13 years 11 months ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
DAC
2002
ACM
14 years 6 months ago
Combined BEM/FEM substrate resistance modeling
For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a B...
Eelco Schrik, N. P. van der Meijs
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
13 years 10 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...