Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
Physical layout generation of RF embedded passive design is not an easy task since the response of a given layout is tightly coupled with the response of the individual components...
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a B...
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...