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» Simulation based deadlock analysis for system level designs
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ICCAD
2010
IEEE
119views Hardware» more  ICCAD 2010»
13 years 3 months ago
Symbolic system level reliability analysis
Abstract--More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such ...
Michael Glaß, Martin Lukasiewycz, Felix Reim...
JNW
2006
108views more  JNW 2006»
13 years 5 months ago
System-Level Fault Diagnosis Using Comparison Models: An Artificial-Immune-Systems-Based Approach
The design of large dependable multiprocessor systems requires quick and precise mechanisms for detecting the faulty nodes. The problem of system-level fault diagnosis is computati...
Mourad Elhadef, Shantanu Das, Amiya Nayak
TVLSI
2010
12 years 12 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
14 years 2 months ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...
SPIN
2012
Springer
11 years 7 months ago
Counterexample Explanation by Anomaly Detection
Since counterexamples generated by model checking tools are only symptoms of faults in the model, a significant amount of manual work is required in order to locate the fault that...
Stefan Leue, Mitra Tabaei Befrouei