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VTS
1999
IEEE
81views Hardware» more  VTS 1999»
13 years 9 months ago
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...
Debashis Nayak, D. M. H. Walker
VTS
1999
IEEE
88views Hardware» more  VTS 1999»
13 years 9 months ago
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venk...
DFT
2003
IEEE
117views VLSI» more  DFT 2003»
13 years 10 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
ISQED
2009
IEEE
126views Hardware» more  ISQED 2009»
13 years 11 months ago
Robust differential asynchronous nanoelectronic circuits
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
Bao Liu
DAC
2010
ACM
13 years 8 months ago
Scalable specification mining for verification and diagnosis
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
Wenchao Li, Alessandro Forin, Sanjit A. Seshia