23 search results - page 3 / 5 » Simultaneous Control of Subthreshold and Gate Leakage Curren... |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...
DT
2007
13 years 5 months ago
2007
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now beco...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...