Sciweavers

12 search results - page 2 / 3
» Simultaneous Placement and Module Optimization of Analog IC'...
Sort
View
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
13 years 10 months ago
Droplet routing in the synthesis of digital microfluidic biochips
same level of system-level CAD support that is now commonplace in the IC industry.Recent advances in microfluidics are expected to lead to sensor systems for high-throughput bioche...
Fei Su, William L. Hwang, Krishnendu Chakrabarty
ESTIMEDIA
2008
Springer
13 years 6 months ago
A framework for memory-aware multimedia application mapping on chip-multiprocessors
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...
Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasric...
DATE
1998
IEEE
91views Hardware» more  DATE 1998»
13 years 9 months ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...
DAC
2008
ACM
14 years 5 months ago
Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This...
Krishna Bharath, Ege Engin, Madhavan Swaminathan
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
13 years 11 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu