33 search results - page 3 / 7 » Simultaneous logic decomposition with technology mapping in ... |
DAC
2010
ACM
13 years 10 months ago
2010
ACM
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
ICCAD
1991
IEEE
13 years 9 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...