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ASPDAC
2010
ACM
105views Hardware» more  ASPDAC 2010»
13 years 2 months ago
Simultaneous slack budgeting and retiming for synchronous circuits optimization
Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang
DAC
2006
ACM
14 years 5 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
DATE
1999
IEEE
127views Hardware» more  DATE 1999»
13 years 9 months ago
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
TCAD
2002
91views more  TCAD 2002»
13 years 4 months ago
Retiming and clock scheduling for digital circuit optimization
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
13 years 10 months ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...