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» Sizing of Processing Arrays for FPGA-Based Computation
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ICPP
2009
IEEE
13 years 2 months ago
Using Subfiling to Improve Programming Flexibility and Performance of Parallel Shared-file I/O
There are two popular parallel I/O programming styles used by modern scientific computational applications: unique-file and shared-file. Unique-file I/O usually gives satisfactory ...
Kui Gao, Wei-keng Liao, Arifa Nisar, Alok N. Choud...
FCCM
2005
IEEE
102views VLSI» more  FCCM 2005»
13 years 10 months ago
A Signature Match Processor Architecture for Network Intrusion Detection
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructu...
Janardhan Singaraju, Long Bu, John A. Chandy
BMCBI
2007
233views more  BMCBI 2007»
13 years 5 months ago
160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)
Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching s...
Isaac T. S. Li, Warren Shum, Kevin Truong
CIMCA
2005
IEEE
13 years 10 months ago
Oscillatory neural network for adaptive dynamical image processing
We develop a biologically motivated oscillatory network model and related dynamical synchronizationbased method of image segmentation. The first version of successive segmentation...
Margarita Kuzmina, Edward A. Manykin
JPDC
2000
141views more  JPDC 2000»
13 years 4 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...