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ENTCS
2010
113views more  ENTCS 2010»
13 years 5 months ago
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
Dan R. Ghica, Alex Smith
MMS
2010
13 years 4 months ago
Asynchronous reflections: theory and practice in the design of multimedia mirror systems
-- In this paper, we present a theoretical framing of the functions of a mirror by breaking the synchrony between the state of a reference object and its reflection. This framing p...
Wei Zhang, Bo Begole, Maurice Chu
ISCAS
2008
IEEE
102views Hardware» more  ISCAS 2008»
14 years 6 days ago
Asynchronous balanced gates tolerant to interconnect variability
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang...
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
13 years 10 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...
HIPEAC
2005
Springer
13 years 11 months ago
Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
Bengu Li, Ganesh Venkatesh, Brad Calder, Rajiv Gup...