107 search results - page 2 / 22 » Smooth switching problem in buffered crossbar switches |
INFOCOM
2007
IEEE
13 years 11 months ago
2007
IEEE
— A good crossbar switch scheduler should be able to achieve 100% throughput and maintain fairness among competing flows. A pure input-queued (IQ) non-buffered switch requires a...
GLOBECOM
2006
IEEE
13 years 11 months ago
2006
IEEE
— Combined input-crosspoint buffered (CICB) packet switches with dedicated crosspoint buffers require a minimum amount of memory in the buffered crossbar of N2 × k × L, where N...
IPPS
2008
IEEE
13 years 11 months ago
2008
IEEE
Buffered crossbar switches are a special type of combined input-output queued switches with each crosspoint of the crossbar having small on-chip buffers. The introduction of cross...
FPGA
2006
ACM
13 years 9 months ago
2006
ACM
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
ICC
2008
IEEE
13 years 12 months ago
2008
IEEE
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...