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» Soft Error Hardening for Asynchronous Circuits
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DATE
2009
IEEE
202views Hardware» more  DATE 2009»
14 years 10 days ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
13 years 12 months ago
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
Natasa Miskov-Zivanov, Diana Marculescu
DDECS
2007
IEEE
143views Hardware» more  DDECS 2007»
13 years 12 months ago
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques
Logic Soft Errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft ...
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Lu...
ICCAD
2004
IEEE
150views Hardware» more  ICCAD 2004»
14 years 2 months ago
Cost-effective radiation hardening technique for combinational logic
— A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates...
Quming Zhou, Kartik Mohanram