35 search results - page 4 / 7 » Soft Error-Aware Power Optimization Using Gate Sizing |
ECCC
2000
13 years 5 months ago
2000
This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve ...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...