35 search results - page 5 / 7 » Soft Error-Aware Power Optimization Using Gate Sizing |
ISVLSI
2007
IEEE
14 years 10 days ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
VLSID
2003
IEEE
14 years 6 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
IPCCC
2007
IEEE
14 years 11 days ago
2007
IEEE
Leakage power is a major concern in current microarchitectures as it is increasing exponentially with decreasing transistor feature sizes. In this paper, we present a technique ca...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...