9 search results - page 2 / 2 » Soft error benchmarking of L2 caches with PARMA |
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Ever scaling process technology makes embedded systems more vulnerable to soft errors than in the past. One of the generic methods used to fight soft errors is based on duplicati...
SC
2009
ACM
13 years 11 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
The need to provide performance guarantee in high performance servers has long been neglected. Providing performance guarantee in current and future servers is difficult because ...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...