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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
13 years 11 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
EUROMICRO
1998
IEEE
13 years 10 months ago
System Level Modelling for Hardware/Software Systems
Industry is facing a crisis in the design of complex hardware/software systems. Due to the increasing complexity, the gap between the generation of a product idea and the realisat...
Jeroen Voeten, P. H. A. van der Putten, Marc Geile...
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 6 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 2 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
MSE
2005
IEEE
148views Hardware» more  MSE 2005»
13 years 11 months ago
Teaching System-Level Design Using SpecC and SystemC
System-level design of embedded computer systems is essential to manage complexity and enhance designer productivity. Viewing designs at t abstraction levels allows developers to ...
Robert D. Walstrom, Joseph Schneider, Diane T. Rov...