67 search results - page 13 / 14 » Software-based instruction caching for embedded processors |
CODES
2004
IEEE
13 years 8 months ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
EMSOFT
2010
Springer
13 years 3 months ago
2010
Springer
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
WORDS
2002
IEEE
13 years 10 months ago
2002
IEEE
The Worst-Case Execution-Time Analysis (WCET Analysis) of program code that is to be executed on modern processors is a highly complex task. First, it involves path analysis, to i...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Power analysis attacks are a type of side-channel attacks that exploits the power consumption of computing devices to retrieve secret information. They are very effective in br...