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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 2 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
SIGMOD
1997
ACM
127views Database» more  SIGMOD 1997»
13 years 9 months ago
Fast Parallel Similarity Search in Multimedia Databases
Most similarity search techniques map the data objects into some high-dimensional feature space. The similarity search then corresponds to a nearest-neighbor search in the feature...
Stefan Berchtold, Christian Böhm, Bernhard Br...
EUROPAR
2011
Springer
12 years 5 months ago
A Bit-Compatible Parallelization for ILU(k) Preconditioning
Abstract. ILU(k) is a commonly used preconditioner for iterative linear solvers for sparse, non-symmetric systems. It is often preferred for the sake of its stability. We present T...
Xin Dong 0004, Gene Cooperman
NOSSDAV
2011
Springer
12 years 8 months ago
A measurement study of resource utilization in internet mobile streaming
The pervasive usage of mobile devices and wireless networking support have enabled more and more Internet streaming services to all kinds of heterogeneous mobile devices. However,...
Yao Liu, Fei Li, Lei Guo, Songqing Chen
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 2 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...