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» Spare-cell-aware multilevel analytical placement
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ICCAD
2006
IEEE
129views Hardware» more  ICCAD 2006»
13 years 11 months ago
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm consi...
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hs...
ISPD
2006
ACM
102views Hardware» more  ISPD 2006»
13 years 11 months ago
A faster implementation of APlace
APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and densi...
Andrew B. Kahng, Qinke Wang
ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
13 years 9 months ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
13 years 11 months ago
Multilevel generalized force-directed method for circuit placement
Automatic circuit placement has received renewed interest recently given the rapid increase of circuit complexity, increase of interconnect delay, and potential sub-optimality of ...
Tony F. Chan, Jason Cong, Kenton Sze
ISPD
2004
ACM
97views Hardware» more  ISPD 2004»
13 years 10 months ago
Implementation and extensibility of an analytic placer
Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently rec...
Andrew B. Kahng, Qinke Wang