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» Sparse Matrix-Vector Multiplication Design on FPGAs
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FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
12 years 5 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
12 years 8 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientiļ¬c and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
ERSA
2010
199views Hardware» more  ERSA 2010»
12 years 1 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
FCCM
2006
IEEE
268views VLSI» more  FCCM 2006»
12 years 9 months ago
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
Yousef El-Kurdi, Warren J. Gross, Dennis Giannacop...
ASAP
2006
IEEE
121views Hardware» more  ASAP 2006»
12 years 7 months ago
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...
Humberto Calderon, Stamatis Vassiliadis
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