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» Spatio-temporal memory streaming
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ANCS
2009
ACM
13 years 2 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
TCAD
2010
124views more  TCAD 2010»
12 years 11 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
CCGRID
2011
IEEE
12 years 8 months ago
High Performance Pipelined Process Migration with RDMA
—Coordinated Checkpoint/Restart (C/R) is a widely deployed strategy to achieve fault-tolerance. However, C/R by itself is not capable enough to meet the demands of upcoming exasc...
Xiangyong Ouyang, Raghunath Rajachandrasekar, Xavi...
DATAMINE
2008
95views more  DATAMINE 2008»
13 years 3 months ago
A dynamic bibliometric model for identifying online communities
Predictive modelling of online dynamic user-interaction recordings and community identifi cation from such data b ecomes more and more imp ortant w ith th e w idesp read use of on...
Xin Wang, Ata Kabán