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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
13 years 11 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
HPCA
2009
IEEE
14 years 4 days ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
CGO
2009
IEEE
14 years 4 days ago
Scenario Based Optimization: A Framework for Statically Enabling Online Optimizations
Abstract—Online optimization allows the continuous restructuring and adaptation of an executing application using live information about its execution environment. The further ad...
Jason Mars, Robert Hundt
CF
2011
ACM
12 years 5 months ago
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazal...
MICRO
1991
IEEE
85views Hardware» more  MICRO 1991»
13 years 8 months ago
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...