9 search results - page 1 / 2 » Specifying the worst case: orthogonal modeling of hardware e... |
ISSTA
2009
ACM
13 years 11 months ago
2009
ACM
During testing, the execution of valid cases is only one part of the task. Checking the behavior in boundary situations and in the presence of errors is an equally important subje...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
IC manufacturing process variations are typically expressed in terms of joint probability density functions (jpdf’s) or as worst case combinations/corners of the device model pa...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In nanometer regime, IC designs have to consider the impact of process variations, which is often indicated by manufacturing/parametric yield. This paper investigates a yield model...