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1999
Tsinghua U.
13 years 9 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
MICRO
2010
IEEE
242views Hardware» more  MICRO 2010»
13 years 3 months ago
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, M...
CF
2005
ACM
13 years 7 months ago
On the energy-efficiency of speculative hardware
Microprocessor trends are moving towards wider architectures and more aggressive speculation. With the increasing transistor budgets, energy consumption has become a critical desi...
Nana B. Sam, Martin Burtscher
PDCN
2007
13 years 6 months ago
Design and evaluation of an auto-memoization processor
This paper describes the design and evaluation of an auto-memoization processor. The major point of this proposal is to detect the multilevel functions and loops with no additiona...
Tomoaki Tsumura, Ikuma Suzuki, Yasuki Ikeuchi, Hir...
ISCA
2006
IEEE
148views Hardware» more  ISCA 2006»
13 years 11 months ago
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range ...
Christopher B. Colohan, Anastassia Ailamaki, J. Gr...