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» Stable and compact inductance modeling of 3-D interconnect s...
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ICCAD
2006
IEEE
133views Hardware» more  ICCAD 2006»
14 years 1 months ago
Stable and compact inductance modeling of 3-D interconnect structures
Recent successful techniques for the efficient simulation of largescale interconnect models rely on the sparsification of the inverse of the inductance matrix L. While there are...
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Ko...
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
13 years 11 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
ASPDAC
2005
ACM
110views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Compact and stable modeling of partial inductance and reluctance matrices
Abstract— The sparsification of the reluctance matrix L−1 (where L denotes the usual inductance matrix L) has been widely used in several recent investigations to make the pro...
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Ko...
ECCV
2010
Springer
13 years 9 months ago
Photo-consistent Planar Patches from Unstructured Cloud of Points
Abstract. Planar patches are a very compact and stable intermediate representation of 3D scenes, as they are a good starting point for a complete automatic reconstruction of surfac...