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» State-based power analysis for systems-on-chip
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PATMOS
2000
Springer
13 years 8 months ago
Early Power Estimation for System-on-Chip Designs
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reo...
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
13 years 10 months ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
TOOLS
2008
IEEE
13 years 11 months ago
A Comparison of State-Based Modelling Tools for Model Validation
In model-based testing, one of the biggest decisions taken before modelling is the modelling language and the model analysis tool to be used to model the system under investigation...
Emine G. Aydal, Mark Utting, Jim Woodcock
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 4 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
MDM
2001
Springer
138views Communications» more  MDM 2001»
13 years 9 months ago
Operating System and Algorithmic Techniques for Energy Scalable Wireless Sensor Networks
An system-level power management technique for massively distributed wireless microsensor networks is proposed. A power aware sensor node model is introduced which enables the embe...
Amit Sinha, Anantha Chandrakasan