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DAC
2007
ACM
14 years 6 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
HPCA
2009
IEEE
14 years 6 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
ISCAPDCS
2004
13 years 7 months ago
FG: A Framework Generator for Hiding Latency in Parallel Programs Running on Clusters
FG is a programming environment for asynchronous programs that run on clusters and fit into a pipeline framework. It enables the programmer to write a series of synchronous functi...
Thomas H. Cormen, Elena Riccio Davidson
AMAST
2008
Springer
13 years 7 months ago
Vx86: x86 Assembler Simulated in C Powered by Automated Theorem Proving
Abstract. Vx86 is the first static analyzer for sequential Intel x86 assembler code using automated deductive verification. It proves the correctness of assembler code against func...
Stefan Maus, Michal Moskal, Wolfram Schulte
JSA
2007
191views more  JSA 2007»
13 years 5 months ago
Automated memory-aware application distribution for Multi-processor System-on-Chips
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
Heikki Orsila, Tero Kangas, Erno Salminen, Timo D....